Experience the thrill of breakthroughs in the dynamic realm of VLSI
I’m thrilled to share my thoughts on some groundbreaking technologies that will reshape our industry. 💡 Let’s talk about PCIe Gen6, CXL 3.0, and UCIe, which I believe are truly disruptive and represent the next level of innovation.
🚀 While PCIe Gen6 may appear as a natural progression from Gen 5, it surpasses previous limits by achieving an impressive throughput of 64 GT/s per lane per direction. What sets PCIe Gen6 apart is its ability to pack multiple TLPs into flits and its seamless integration with cache-coherent fabrics like CXL. This makes PCIe a perfect ally for the CXL protocol, which can reside in the Transaction Layer of the PCIe protocol, leveraging the advantages of PCIe (including UCIe) to the fullest. 🚀
💡 CXL 3.0 introduces protocols such as CXL.mem and CXL.cache, taking cache-coherence all the way to the rack level from the node. This achievement enables a remarkable concept called CDI (Composable Disaggregated Infrastructure), allowing us to work with larger pools of DRAMs and Accelerators in unprecedented ways. CDI offers a grand, cache-coherent virtualization of IOs, driving remarkable advancements in our field. 💡
🌟 UCIe, the die2die interconnect, enables standardization of Chiplet interfaces. Suddenly, within the same package, we can integrate chiplets from multiple vendors, fulfilling our dream of achieving top performance and value without being locked into a single vendor due to interoperability issues. The possibilities are endless! 🌟
Looking ahead, these transformative technologies, coupled with ever-scaling [G/LP] DDRs, will have a dramatic impact on the underlying structure of DCs/Clouds at the leaf level of the Clos architecture (Server nodes). Expect remarkable improvements in “performance per watt” and more efficient utilization of server resources in the coming years. 🚀
Chandra Mallela
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